Problem with delay DIR-STEP

ytliu · Posted at 2018-8-10 07:22:02

Last edited by ytliu In 2018-8-10 09:22 Editor

The current motor drive signal generation logic is: in each signal processing period (t), the DIR signal is first established, and the PLU signal rises at time #416 and falls at t/2.(see Attachment)

I will make the following changes:
The current signal processing period DIR signal does not change, the PLU signal rises at time 0, and falls at t/2;
Otherwise, proceed as before.

Since the motion of the system is planned, the speed at which the direction changes is generally low. At this time, t is relatively large, so the case of #416>t/2 does not occur.

This should be a relatively simple way to solve this problem.

I have already ordered LEADSHINE 556 and I will verify it.

ytliu · Posted at 2018-8-11 06:24:11

Nikolay81 Posted at 2018-8-11 01:14
I wrote a new article for you.
I hope it will help you better understand the reasons for missing t ...

Thank you very much for your analysis of this issue, I will use the first way you said to make changes.

ytliu · Posted at 2018-8-15 06:25:55

Nikolay81 Posted at 2018-8-14 18:06
While Ytliu tries (or does not try) to implement the delay of DIR-STEP programmatically, I'll try to ...

Looking forward to your results. In addition, I have completed the logic design, the test results are satisfactory, #416 set to 7000ns can meet most of the drive requirements. Thank you again for your excellent work.

ytliu · Posted at 2018-8-20 09:13:33

Biligo Posted at 2018-8-19 04:37
Dear gurus, I would like to ask for your advice. Which drivers would you recommend purchasing? Which ...

The tb6600 driver can be used with confidence, and we have a lot of users using it. If lost steps occurs during processing, change the pulse level polarity in ddcsv.

ytliu · Posted at 2018-9-2 07:53:58

Thank you for your excellent work. I saw the schematic and I think it has no defects. This circuit should be very good at solving the problem of losing steps.
DDCSV has built-in FPGA, I added delay logic on FPGA, it has been tested for a while, and it works well so far.

ytliu · Posted at 2018-9-4 06:23:03

Nikolay81 Posted at 2018-9-2 17:26
And how can "ordinary people" benefit from the results of your work?
Will it be possible, through ...

Your idea is correct, users can't update fpga themselves.

ytliu · Posted at 2018-9-4 21:44:48

Nikolay81 Posted at 2018-9-4 14:47
Excuse my incomprehensibility. I correctly understood that now all DDCSV will be produced with a n ...

Users cannot update the fpga firmware themselves.
After the detailed test is completed, we will upgrade the fpga firmware in the new production ddcsv system.
In the new fpga firmware,parameter #416 can be set to any number up to 1ms.

ytliu · Posted at 2018-9-8 23:01:43

Lukasz Posted at 2018-9-8 16:10
Hello Ytliu,

Is it possible to program the FPGA by using external tool (eg. USB blaster) and JTAG c ...

Sorry, we are unable to provide firmware for fpga.

ytliu · Posted at 2018-9-27 06:56:58

bgarroweer Posted at 2018-9-26 16:08
To ytliu:
Did I understand right that the problem cannot be solved by downloading Upgrading Code fro ...

Hi bgarroweer!

Your understanding is correct. However, in most cases, the problem of out-of-step is solved by adjusting the parameters.

In addition, we will soon release a new version of the DDCSV system, this issue will be fixed.

ytliu · Posted at 2019-1-10 17:40:53

Problem with delay DIR-STEP

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