Problem with delay DIR-STEP

ytliu · Posted at 2018-8-8 06:08:45

Last edited by ytliu In 2018-8-8 06:33 Editor

Nikolay81 Posted at 2018-8-8 01:37
The CW / CCW mode unfortunately does not work properly.
In this mode, depending on the direction o ...

Sorry, I made a mistake. Parameter #230-#233 If configured as 1, the output mode is A/B phase mode, the controller does not support CW/CCW output mode.

Nikolay81 · Posted at 2018-8-8 15:16:58

Does the controller not support CW / CCW for hardware reasons?
Or will it be possible to add CW / CCW support in a programmatic way over time?

ytliu · Posted at 2018-8-8 17:10:07

Nikolay81 Posted at 2018-8-8 15:16
Does the controller not support CW / CCW for hardware reasons?
Or will it be possible to add CW / CC ...

Yes, the controller cannot support CW/CCW due to hardware.

Nikolay81 · Posted at 2018-8-9 04:08:35

ytliu Posted at 2018-8-8 17:10
Yes, the controller cannot support CW/CCW due to hardware.

I understood why steps are lost and how to fix it. Please read the article in the attached file. Also there is the original article in the Russian language. Maybe it will be interesting to someone.
I could not attach the file to the message, and put it on Google Drive
https://drive.google.com/open?id ... zTQGxHBonuvyN_-mcTn

ytliu · Posted at 2018-8-9 06:15:41

Have you replaced the resistor? The problem now is that the optocoupler does not work properly during high frequency operation due to excessive series resistance.

ytliu · Posted at 2018-8-9 06:48:27

ytliu Posted at 2018-8-9 06:15
Have you replaced the resistor? The problem now is that the optocoupler does not work properly durin ...

Ia=(5V-0.7V)/(270+100)=11.6ma < 16ma

When operating at high frequencies, the logic signal current cannot meet the requirements, resulting in lost steps.

Nikolay81 · Posted at 2018-8-9 14:37:46

Last edited by Nikolay81 In 2018-8-9 14:42 Editor

ytliu Posted at 2018-8-9 06:48
Ia=(5V-0.7V)/(270+100)=11.6ma < 16ma

When operating at high frequencies, the logic signal current ...

Thank you. I also read the instructions to these drivers and consulted with familiar electronics engineers.
I will certainly remove the resistors today. Just for the experiment.
This takes time. In this situation, the dismantling of the controller is rather complicated.
The result "before" and "after", I will describe in detail.
But, even with the help of logic and mathematics, one can understand that this can improve the problem but not solve it.
Because increasing the delay DIR-STEP solves the problem completely. Without removing the resistors.In this, I was convinced yesterday on my experience.
In the Purelogic controllers, there were no resistors at the outputs, but they still skipped the steps with the Leadshine drivers.
While they did not increase the delay of DIR-STEP. Then the problem immediately decided.
Still, the question arises: why did they even add the "Time interval between DIR & pulse" setting, if its value can not be changed?
After all, if there is something, it should work. If it obviously does not work, it should be removed, so as not to embarrass the users.

Perhaps I do not understand something. Please tell me how difficult it is to fix the bug with the setting "Time interval between DIR & pulse"?
If it takes a very long time, or is impossible at all - I'll understand.
Then we will look for "ways to bypass" the problem.

ytliu · Posted at 2018-8-9 23:20:58

Nikolay81 Posted at 2018-8-9 14:37
Thank you. I also read the instructions to these drivers and consulted with familiar electronics en ...

I have encountered many customers who have lost steps due to the "Time interval between DIR & pulse". By changing the pulse level, this problem can be solved very well.

As for the problem you are currently experiencing, you must first replace the resistor, and subsequent analysis is meaningful. After replacing the resistor, if there is still a problem, I will purchase LEADSHINE 556 and verify it myself.

Since this update involves hardware logic, I have to be very cautious, please understand.

Nikolay81 · Posted at 2018-8-10 05:49:44

ytliu Posted at 2018-8-9 23:20
I have encountered many customers who have lost steps due to the "Time interval between DIR & puls ...

I replaced the resistors with jumpers.
I had resistors 100 ohms.
The driver input circuit diagram is incorrect.
Everything is completely different there.
Perhaps this scheme is version 1.0. And I have version 2.2.

Before and after removing the resistors, I shot the oscillograms, between the different terminals of the optocoupler with a logic output of 6N137.
This is a very common optocoupler. Datasheet on it, you can easily find it in Google.

Conclusion - nothing has changed. Perhaps there was a little more interference. In general, the signal at the output of the optocoupler has a lot of noise.
Unfortunately, the theory of improving the performance of the optocoupler, after shunting the resistor, was not correct. You can not remove the resistor.

I uploaded a waveform to Google Drive. They can be opened by the program "Multi VirAnalyzer".
You can download it here: http://english.instrustar.com/upload/image//English%20Version(3_10_7_1).zip

In some oscillograms, I was wrong with the division of the probe (put X10). There, the voltage should be divided by 10.
I think everything will be clear.

In some oscillograms, a different frequency.
This has been the case before. Often on the same programs, there is a different frequency. I do not know why this happens.

I will write more in detail tomorrow. It's very late now.

Here is a link to oscillograms:
https://drive.google.com/open?id ... dpnRbFb1pjd4J3THV3r

ytliu · Posted at 2018-8-10 07:22:02

Last edited by ytliu In 2018-8-10 09:22 Editor

The current motor drive signal generation logic is: in each signal processing period (t), the DIR signal is first established, and the PLU signal rises at time #416 and falls at t/2.(see Attachment)

I will make the following changes:
The current signal processing period DIR signal does not change, the PLU signal rises at time 0, and falls at t/2;
Otherwise, proceed as before.

Since the motion of the system is planned, the speed at which the direction changes is generally low. At this time, t is relatively large, so the case of #416>t/2 does not occur.

This should be a relatively simple way to solve this problem.

I have already ordered LEADSHINE 556 and I will verify it.

Problem with delay DIR-STEP

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